1. Field of the Invention
The present invention relates to compensation for a variation in power supply voltage and a variation in temperature in a delay circuit.
This application is counterparts of Japanese patent applications, Serial Number 190964/2005, filed on Jun. 30, 2005 and 147587/2006, filed on May 29, 2006, the subject matter of which are incorporated herein by reference.
2. Description of the Related Art
As delay circuits for signal delay, each configured using a plurality of stages of inverters, there have heretofore been known ones described in, for example, patent documents 1 and 2 (Japanese Laid Open Patent Application No. Hei 7 (1995)-38394 and Japanese Laid Open Patent Application No. Hei 9 (1997)-214306)
FIG. 2 is a circuit diagram showing a configurational example of the conventional delay circuit described in the patent document 1.
The delay circuit shown in FIG. 2 is a circuit which, when an input signal VI is transitioned from a high level (hereinafter called “H” level) to a low level (hereinafter called “L” level), produces or forms a desired delay time and outputs an output signal VO therefrom. The present delay circuit comprises inverter circuits of four stages which comprise P channel MOS transistors (hereinafter called “PMOSs”) and N channel MOS transistors (hereinafter called “NMOSs”) and which delay the input signal VI and output an output signal VO, a correction circuit 1 which supplies a control signal NO for delay time correction to the NMOSs constituting the inverter circuits of four stages, and a correction circuit 2 which supplies a control signal NO for delay time correction to the PMOSs constituting the inverter circuits of four stages.
The inverter circuits of four stages comprise a modified inverter I1 corresponding to a first stage which outputs a signal Va obtained by inverting and delaying an input signal VI, a modified inverter I2 corresponding to a second stage which outputs a signal Vb obtained by inverting and delaying the signal Va, a modified inverter I3 corresponding to a third stage which outputs a signal Vc obtained by inverting and delaying the signal Vb, and a modified inverter I4 corresponding to a fourth stage which outputs an output signal VO obtained by inverting and delaying the signal Vc.
The first-stage modified inverter I1 has a PMOS p2 whose gate electrode (hereinafter called simply “gate”) is controlled by a control signal PO outputted from the correction circuit 2, a PMOS p1 whose gate is controlled by the input signal VI, and an NMOS n1 of which the gate is controlled by the input signal VI. Respective source electrodes (hereinafter called simply “sources”) of the these PMOSs p2 and p1 and NMOS n1 and respective drain electrodes (hereinafter called simply “drains”) thereof are respectively connected in series between a power supply terminal (hereinafter called “VDD terminal”) to which a power supply voltage VDD is applied, and a ground terminal (hereinafter called “VSS terminal”) to which a ground voltage VSS is applied.
The second-stage modified inverter I2 has a PMOS p3 of which the gate is controlled by the signal Va, an NMOS n3 whose gate is controlled by the signal Va, and an NMOS n2 whose gate is controlled by the control signal NO outputted from the correction circuit 1. The sources and drains of these PMOS p3 and NMOSs n3 and n2 are series-connected between the VDD terminal and the VSS terminal.
The third-stage modified inverter I3 has a PMOS p5 whose gate is controlled by the control signal PO, a PMOS p4 whose gate is controlled by the signal Vb, and an NMOS n4 whose gate is controlled by the signal Vb. The respective sources and drains of these PMOSs p5 and p4 and NMOS n4 are connected in series between the VDD terminal and the VSS terminal.
The fourth-stage modified inverter I4 has a PMOS p6 whose gate is controlled by the signal Vc, an NMOS n6 whose gate is controlled by the signal Vc, and an NMOS n5 whose gate is controlled by the control signal NO. The respective sources and drains of these PMOS p6 and NMOSs n6 and n5 are connected in series between the VDD terminal and the VSS terminal.
The correction circuit 1 has a resistor r1, an internal node N1 used to output the control signal NO, and an NMOS n7 whose gate is controlled by a signal CE. These resistor r1, internal node N1 and NMOS n7 are connected in series between the VDD terminal and the VSS terminal. The signal CE supplied to the gate of the NMOS n7 serves as the power supply voltage VDD during operation and serves as the ground voltage VSS at standby.
The correction circuit 2 has a PMOS p7 whose gate is controlled by a signal /CE, an internal node N2 used to output the control signal PO, and a resistor r2. These PMOS p7, internal node N2 and resistor r2 are connected in series between the VDD terminal and the VSS terminal. The signal /CE supplied to the gate of the PMOS p7 serves as the ground voltage VSS during operation and serves as the power supply voltage VDD at standby.
The operation of the delay circuit shown in FIG. 2 will next be explained.
When the input signal VI falls from an “H” level to an “L” level, the respective input signals Va and Vc of the modified inverters I2 and I4 are respectively transitioned from an “L” level to an “H” level. At this time, the dimensions of the NMOSs n2 and n5 and the voltage of the control signal NO of the correction circuit 1 are set in such a manner that the values of currents that the modified inverters I2 and I4 supply to the VSS terminal side are respectively determined by the NMOS n2 and the NMOS n5.
When the threshold voltage Vtn of each NMOS is reduced due to a process variation, the voltage of the control signal NO of the correction circuit 1 is lowered. Therefore, the effect of decreasing an on resistance value by the reduction in the threshold voltage Vtn of each of the NMOSs n2 and n5 and the effect of increasing an on resistance value by a reduction in gate voltage of each NMOS are cancelled out. Hence, there is little difference between delay times of the modified inverters I2 and I4 as compared with the case in which the threshold voltage Vtn is of a standard value. When the threshold voltage Vtn of each NMOS is large, the effect of increasing an on resistance value by the increase in the threshold voltage Vtn of each of the NMOSs n2 and n5, and the effect of decreasing an on resistance value by a rise in gate voltage of each NMOS are cancelled out. Hence, there is little difference between the delay times as compared with the case in which the threshold voltage Vtn is of a standard value. Consequentially, even though the threshold voltage Vtn of each NMOS varies depending upon the process variation, the difference in delay time little occurs between the modified inverters I2 and I4.
When the ambient temperature is low, the effect of decreasing on resistance values of the NMOSs n2 and n5 and the effect of increasing their on resistance values by a reduction in the voltage of the control signal NO are cancelled out. When the ambient temperature is high, the effect of increasing the on resistance values of the NMOSs n2 and n5 and the effect of decreasing their on resistance values by an increase in the voltage of the control signal NO are cancelled out. As a result, there is little difference in delay time between the modified inverters I2 and I4 where the ambient temperature is low and high.
Further, since the modified inverter I1 and the modified inverter I3 also generate effects similar to the modified inverters I2 and I4 by means of the correction circuit 2, there is little difference in delay time due to the process variation and the variation in ambient temperature.
Thus, the conventional delay circuit shown in FIG. 2 compensates for a variation in delay time due to the process variation and the variation in ambient temperature and obtains a predetermined delay time at all times.
However, such a conventional delay circuit as shown in FIG. 2 is accompanied by a problem that although the variation in delay time due to the process variation and the variation in ambient temperature is compensated for, the delay time also varies when the power supply voltage VDD varies.